Normal Computing built a 580,000 line open source chip design simulator in 43 days to escape roughly $10,000 per core commercial tools, and the more durable story is the verification gap the simulator was built to plug, with the team's own agent coding benchmark scoring roughly…
In 43 days, a team at Normal Computing built a 580,000-line open-source Verilog simulator, the kind of chip-design tool that commercial vendors typically sell for roughly $10,000 per core license. They did it because the alternative, trusting AI-generated chip designs against a commercial verification stack priced in the same range, had become the riskier option. The chip they taped out at the same time, the CN101, is the more photogenic artifact. The verification gap underneath it is the more durable story.
The CN101 tape-out announcement is what most readers will have seen first, because Normal Computing framed it as the world's first thermodynamic computing chip. That framing is the company's claim, not an independent benchmark. IEEE Spectrum's analysis places the design in a longer-running academic conversation about stochastic and RLC-based prototypes, which is the right context for treating the "world's first" language as a tape-out priority claim rather than a settled engineering fact.
What the chip actually is, in plain terms: a probabilistic AI accelerator built around resistor-inductor-capacitor unit cells whose switched-capacitance coupling is meant to let thermal noise do the matrix math the chip is designed to perform. Thermodynamic computing, in this framing, is the idea of building the math around the physics rather than fighting it. Founder Thomas Ahle, previously a mechanistic-interpretability researcher at Facebook AI, has described the device in a long Machine Learning Street Talk appearance as an answer to AI workloads that look more like solving noisy linear systems, sometimes modeled as stochastic differential equations that bake randomness in rather than averaging it out, than running dense matrix multiplies on a GPU.
Normal Computing says it has raised more than $85 million to date, including a $50 million round led by Samsung Catalyst in March 2026. The Fortune piece framed the round as a bet that the next AI-silicon efficiency gains will come from co-designing the math and the physics, not from another incremental shrink on a standard process node. The same company also sells Normal EDA, an AI-accelerated commercial EDA stack it says is in production at large semiconductor customers, which puts Normal Computing in the awkward position of being both a chip startup and a tool vendor competing with the very vendors it built its own simulator to escape.
The harder thread is the DIY verification stack. Ahle and his team wrote a custom open-source Verilog simulator (Verilog being the hardware-description language that chip designs are written in, the closest thing silicon has to source code) in 43 days, per the company's engineering blog. The post says the agent-written simulator reached 580,000 lines, large enough to host the CN101 design and verification flow that the team did not want to trust to commercial EDA. The motivation, as the team describes it, is that commercial verification tools are priced and architected for designs that a human engineer has walked through line by line. Once a model is generating most of the Verilog, that contract quietly breaks.
This is what Ahle has called "understanding debt" in the podcast: code that nobody on the team has read end to end, with a test pass rate that is high enough to ship and low enough to be wrong. The cost of being wrong in silicon is unusual. A fabricated bug in a chip that has already been taped out (tape-out being the final, non-undoable step of sending a design to a foundry for manufacturing) can erase the engineering time and the mask cost of the entire run. Against that, "passes 70% of tests" is not a number. It is a coin flip with a chip-sized loss on one side.
ProgramBench, Ahle's own benchmark, puts a number on the structural risk. In the podcast discussion, he describes ProgramBench as a test that asks an AI agent to reconstruct a program from its own test suite, a proxy for the agent's ability to understand a codebase well enough to maintain it. The team's reported result on that benchmark is roughly 0%. The honest read of that number is not that the field is broken. It is that the verification problem is structural. Agents can write a lot of code, and very little of that code is provably the code the team asked for.
Normal Computing's response, beyond the open-source simulator, is a formal-methods layer. It includes auto-formalization in Lean, a proof assistant that lets engineers write machine-checkable mathematical specifications of what a piece of hardware is supposed to do, and tooling modeled on the AlphaProof approach used at Google DeepMind, where a model produces a formal proof of correctness rather than a passing test suite. The team has also leaned on Petri nets and TLA+, two formal-spec languages used to model concurrency and state machines. None of that is novel in formal methods. What is novel is the integration: a tape-out path that treats AI-written Verilog as an untrusted input and a formally specified chip as the artifact that gets sent to the foundry.
That integration is the bet Samsung Catalyst is underwriting. The Fortune report frames the round as a foundry investor hedging on the assumption that AI-generated silicon will need exactly this kind of verification infrastructure before it can be trusted in production. Whether that bet pays off will depend less on the CN101's benchmarks and more on whether Normal EDA picks up customers who are not the parent company.
A note on sourcing: the most detailed public account of Ahle's thinking is the Machine Learning Street Talk episode that anchors this piece. Normal Computing paid the podcast's production and travel costs; MLST retained full editorial control, and the company did not see or discuss the episode before publication.
Three things will tell us whether the verification story holds up. First, an independent customer or benchmark for Normal EDA, which would convert a company-sourced production claim into a market signal. Second, a peer-reviewed or third-party test of the CN101 that goes beyond Normal Computing's own characterization, ideally one that benchmarks a thermodynamic primitive against a comparable GPU or TPU kernel on the same workload. Third, the next round of ProgramBench results from outside the company, which is what will tell the field whether Ahle's 0% is a property of his benchmark or a property of the agentic-coding moment.
The chip is real silicon, taped out, with a press release to prove it. The verification gap is the more interesting question, and the one the next year of AI-generated chip design is going to have to answer with more than test-pass rates.